1. Field
Embodiments described in the present specification relate to an electrically rewritable nonvolatile semiconductor memory device.
2. Description of the Related Art
A memory cell array in a NAND-type flash memory is configured as an arrangement of NAND cell units, each of the NAND cell units having a plurality of memory cells connected in series. Both ends of a NAND cell unit are connected to a bit line and a source line, respectively, via select gate transistors. The control gate electrodes of memory cells in each NAND cell unit are connected to different word lines. In each NAND cell unit, a plurality of memory cells are connected in series, sharing a source and a drain with one another. In NAND-type flash memory, these memory cells share select gate transistors, associated bit-line or source-line contacts, and so on. This can reduce the size of a unit memory cell. Furthermore, device regions for word lines, memory cells, and so on, in the NAND-type flash memory are configured close to a simple stripe pattern. This is suitable for shrinking and allows large capacity flash memory to be realized.
In NAND-type flash memory, data write and erase are performed by causing FN tunnel current to flow through many cells at the same time. Specifically, data write is performed on a page basis, where a set of memory cells sharing one word line represents one page. After a data write operation, a verify read (write verify) operation is performed to verify whether data is accurately written to the memory cells or not. As a result of the write verify operation, if it is determined that data is not written to the memory cells satisfactorily, then similar write operations and write verify operations are repeated, raising a write pulse voltage in stages (step-up).
In addition, data erase in NAND-type flash memory is performed on a block basis, where a block is defined as a set of NAND cell units sharing word lines and select gate lines. In addition, when data erase is performed in blocks in the NAND-type flash memory, a verify read (erase verify) operation is performed to verify whether a memory cell reaches an erase state or not, that is, whether a threshold voltage of the memory cell falls within a certain value or not. As a result of the erase verify operation, if it is determined that erase is not performed satisfactorily, then similar erase operations and erase verify operations are repeated, raising an erase voltage in stages (step-up).
Incidentally, when the write/erase operations are repeatedly performed on one memory cell, a tunnel insulating film in the memory cell gradually degrades, resulting in a drop in reliability of the NAND-type flash memory. Therefore, stress on memory cells due to write and erase voltages should preferably be reduced as much as possible. Reducing stress on the memory cells improves reliability of the NAND-type flash memory and contributes to a longer lifetime of the memory cells.